1. Field of the Invention
The present invention relates to a priority order decomposing apparatus removing all "1" s other than a bit whose priority order is the highest out of an input of a plurality of bits.
2. Description of the Prior Art
The priority order decomposing apparatus as described above performs processing such that, for example, in the case where an eight-bit input is (00011010), (00010000) is obtained as an output with the highest-order bit "1" left intact and the other bits set to "0". This means that this apparatus is a circuit with the highest-order bit whereto "1" is set, among an input data made effective and the other bits whereto "1" s are set rewritten into "0" s.
FIG. 1 is a circuit diagram showing a n-bit priority order decomposing apparatus. An n-bit input X.sub.n-1, X.sub.n-2, X.sub.n-3, X.sub.n-4, . . . X.sub.1, X.sub.0 is converted into an n-bit output Z.sub.n-1, Z.sub.n-2, Z.sub.n-3, Z.sub.n-4. . . Z.sub.1, Z.sub.0 by n-1 inclusive-or circuits Y.sub.n-2, Y.sub.n-3, Y.sub.n-4, . . . Y.sub.1, Y.sub.0 and n-1 exclusive-or circuits W.sub.n-2, W.sub.n-3, W.sub.n-4, . . . W.sub.1, W.sub.0. Each of the input data X.sub.n-2, X.sub.n-3, X.sub.n-4, . . . X.sub.1, X.sub.0 becomes one input of each of the inclusive-or circuits Y.sub.n-2, Y.sub.n-3, Y.sub.n-4, . . . Y.sub.1, Y.sub.0, and the highest-order input data X.sub.n-1 becomes the other input of each of the inclusive-or circuit Y.sub.n-2 and the exclusive-or circuit W.sub.n-2. Also, an output of each of the inclusive-or circuits Y.sub.n-2, Y.sub.n-3, Y.sub.n-4, . . . Y.sub.1 Y.sub.0 becomes one input of each of the exclusive-or circuits W.sub.n-2, W.sub.n-3, W.sub.n-4, . . . W.sub.1, W.sub.0 respectively. An output of each of the other exclusive-or circuits Y.sub.n-2, Y.sub.n-3, Y.sub.n-4, . . . Y.sub.1 excluding Y.sub.0 becomes the other input of each of the inclusive-or circuits Y.sub.n-3, Y.sub.n-4, . . . Y.sub.1, Y.sub.0 of the low-order-bit side and the other input of each of the exclusive-or circuits W.sub.n-3, W.sub.n-4, . . . W.sub.1, W.sub.0, respectively. Then, respective outputs of the exclusive-or circuits W.sub.n-2, W.sub.n-3, W.sub.n-4, . . . W.sub.1, W.sub.0 are taken as the outputs of this priority order decomposing apparatus Z.sub.n-2, Z.sub.n-3, Z.sub.n-4, . . . Z.sub.1, Z.sub.0. Also, the highest-order input data X.sub.n-1 is taken intact as the output data Z.sub.n-1.
In accordance with such a configuration, data going through the inclusive-or circuits Y.sub.n-2, Y.sub.n-3, Y.sub.n-4, . . . Y.sub.1, Y.sub.0 become data wherein bits following the highest-order "1" are all set to "1". This means that if an input data is (00011010), it becomes (00011111). Subsequently, when the data go through the exclusive-or circuits W.sub.n-2, W.sub.n-3, W.sub.n-4, . . . W.sub.1, W.sub.0, only the output of the circuit whereto "0" and "1" are input becomes "1", and therefore the bit of the highest-order "1" is left intact and the other bits become "0". Accordingly, (00010000) is obtained as an output.
In the priority order decomposing apparatus as described above, propagations of signal by the inclusive-or circuits Y.sub.n-2, Y.sub.n-3, Y.sub.n-4, . . . Y.sub.1, Y.sub.0 produced, and therefore the apparatus has a difficulty that the operating speed is slow and the difference in the operating speeds between the high-order bit and the low-order bit becomes larger as the number of bits increases.